The present invention relates to a technique of writing data into a semiconductor memory device.
FIG. 1 shows a first example of a conventional DRAM.
A row decoder 11 is provided at a row-directional end portion (i.e., an end portion in a direction in which word lines extend) of a memory cell array 10. Row address signals are input to the row decoder via a row address buffer 12.
A row address strobe signal/RAS is input to a row system control circuit 13. A word line control circuit 14 is controlled by an output signal from the row system control circuit 13 and supplies a high potential to a word line of memory cell array 10, which is selected by the row address signal.
A sense amplifier 15 is provided at a column-directional end portion (i.e., an end portion in a direction in which bitline pairs extend) of memory cell array 10. The sense amplifier 15 is activated and deactivated by a sense amplifier control circuit 16.
The amplifier control circuit 16 is operated on the basis of an output signal SEN from the word line control circuit 14. Specifically, when a row of the memory cell array 10 has been selected and a high potential has been applied to the word line, output signals SAP and BSAN for activating the sense amplifier 15 are output.
A column address signal is input to a column decoder 18 via a column address buffer 17. Based on the column address signal, the column decoder 18 opens and closes a column select gate 19.
A data bus (hereinafter referred to as "DQ bus") 20 serves as a data path between the column select gate 19 and a data input/output (I/O) buffer 21.
FIG. 2 shows in detail the layout of the memory cell array 10, sense amplifier 15 and column select gate 19 shown in FIG. 1.
The memory cell array 10 comprises an n-number of blocks BK1, BK2, . . . , BKn. The number of bits permitting simultaneous read/write is an n (bits) (1-bit.times.n structure). The blocks BK1, BK2, . . . , BKn have the same structure.
Word lines 24 extending from the row decoder 11 are arranged on the blocks BK1, BK2, . . . , BKn and connected to a plurality of memory cells 23 belonging to the same row of the memory cell array 10.
Each block has four columns C0 to C3. Each column comprises a bitline pair. A plurality of memory cells 23 belonging to the same column are connected to the bitline pair 22.
One end of the bitline pair 22 of each of columns C0 to C3 is connected to one of data line pairs (hereinafter referred to as "DQ line pairs") 20-1 to 20-n via one of sense amplifiers 15-0 to 15-3 and one of column select gates 19-0 to 19-3.
The sense amplifiers 15-0 to 15-3 are activated and deactivated by control signals SAP and BSAN.
The column select gates 19-0 to 19-3 are opened and closed by column select signals CSL0 to CSL3 output from the column decoder. In each block, one column is selected. Thus, one of the four column select gates 19-0 to 19-3 is turned on. The column select gates 19-0 to 19-3 are constituted by, for example, N-channel MOS transistors.
An n-number of DQ line pairs 20-1 to 20-n extend from the n-number of blocks BK1, BK2, . . . , BKn. The DQ bus 20 comprises the n-number of DQ line pairs 20-1 to 20-n.
In the DRAM having the above structure, when data is to be read out, a row address signal is supplied to the row decoder 11. The row decoder 11 applies a high potential to a word line (row) designated by the row address signal, thereby activating the word line.
In each of blocks BK1, BK2, . . . , BKn, data of the memory cells connected to activated word lines are transferred to the sense amplifiers 15-0 to 15-3 corresponding to the columns C0 to C3, and are latched.
Then, the column select gate, 19-0 to 19-3, of the column, C0 to C3, designated by the column address signal is turned on, and the data of the sense amplifier, 15-0 to 15-3, connected to this column, C0 to C3, is led to the I/O buffer 21 via the DQ line pair, 20-1 to 20-n.
As is shown in FIG. 3, when data is to be written, the row address signal is at first supplied to the row decoder. The row decoder applies a high potential to the word line (row) Wli designated by the row address signal, thereby activating the word line WLi.
In each of the blocks BK1, BK2, . . . , BKn, data of the memory cells connected to the activated word line WLi is led to the sense amplifiers 15-0 to 15-3 of the columns C0 to C3. When the control signal SEN has been set at a high potential, the control signal SAP at a high potential and the control signal BSAN at a low potential, the sense amplifier is activated and the potential of bitline pair BLj, BBLj is amplified.
Thereafter, one of the column select gate of the columns C0 to C3, designated by the column address signal is turned on, and write data is led from the I/O buffer to the designated one of columns C0 to C3, via the DQ line pair.
At this time, the following problem will occur if the write data differs from the data in the memory cells 23 belonging to the designated row and column.
In the designated one of columns C0 to C3, data (e.g. "0") of memory cell 23 is latched and then write data (e.g. "1") is latched. Accordingly, the data of the sense amplifier of the designated one of columns C0 to C3 must be inverted by the write data. The time (write data) needed to invert the data is very long, and this prevents high-speed data write.
FIG. 4 shows an example in which the data write time in the DRAM shown in FIG. 1 is decreased by specially setting the timing for data write.
At first the row address signal is supplied to the row decoder. The row decoder applies a high potential to the word line (row) WLi designated by the row address signal, thereby activating the word line WLi. In each block, BK1, BK2, . . . , BKn, the data of the memory cells connected to the activated word line WLi is led to the sense amplifiers corresponding to the columns C0 to C3.
When a column select line CSLj of one of the columns C0 to C3, designated by the column address signal has been set at a high potential, the column select gate of the associated column is turned on, and the write data is delivered to the sense amplifier of one of the columns C0 to C3.
At this time, since the sense amplifier has not been activated, the potential of bitline pair BLj, BBLj is inverted in a short time, even if the write data differs from the data in the memory cells.
When the control signal SEN has been set at a high potential, the control signal SAP at a high potential and the control signal BSAN at a low potential, the sense amplifier is activated and the potential of bitline pair BLj, BBLj is amplified. Thus, the data write in the memory cells is completed.
However, in the above-described timing, the word line WLi is designated, the sense amplifiers of all columns are activated.
Accordingly, in the first write for the first column after the word line WLi has been designated, the write time is reduced. However, in the second write for the second column after the first write, the write time may increase.
Specifically, in the second write, since the sense amplifiers of all columns were already activated, if the write data differs from the data of the memory cells, a long time is needed to invert the potential of the bitline pair BLj, BBLi.
FIG. 5 shows a second example of the conventional DRAM.
In the DRAM of the second example, write data to be written in all columns is latched in a data latch circuit, and the write data is led to the sense amplifier. Then, the sense amplifiers of all columns are activated and at the same time the write data is written in all columns.
A row decoder 11 is provided at a row-directional end portion of a memory cell array 10. A row address signal is input to the row decoder 11 via a row address buffer 12.
A row address strobe signal/RAS is input to a row system control circuit 13. A word line control circuit 14 is controlled by an output signal from the row system control circuit 13 and applies a high potential to a word line of the memory cell array 10, which has been selected by the row address signal.
A sense amplifier 15 is provided at a column-directional end portion of the memory cell array 10. The sense amplifier 15 is activated and deactivated by a sense amplifier control circuit 16.
The sense amplifier control circuit 16 is operated on the basis of an output signal SEN from the word line control circuit 14. Specifically, when a row of the memory cell array 10 is selected and a high potential is applied to the word line, output signals SAP and BSAN for activating the sense amplifier 15 are output.
A column address signal is input to a column decoder 18 via a column address buffer 17. Based on the column address signal, the column decoder 18 opens and closes a column select gate 19.
A DQ bus 20 serves as a data path between the column select gate 19 and a data input/output (I/O) buffer 21.
A data latch circuit 25 and a transfer gate 26 are connected between the sense amplifier 15 and column select gate 19. The data latch circuit 25 can latch input/output data of all columns. The transfer gate 26 serves as a data transfer path between the sense amplifier 15 and data latch circuit 25. The data transfer is enabled/disabled by the opening/closing of the transfer gate 26.
A transfer gate control signal is input to the transfer gate control circuit. Based on the transfer gate control signal, the transfer gate control circuit 27 controls the transfer of data by the transfer gate 26.
FIG. 6 is a timing chart illustrating the operational timing at a data write operation in the DRAM shown in FIG. 5.
At first, a row address signal is supplied to the row decoder. The row decoder then applies a high potential to the word line (row) WLi designated by the row address signal, thereby activating the word line WLi. In each of the blocks BK1, BK2, . . . , BKn, the data of memory cells connected to the activated word line WLi is led to the sense amplifiers of the columns C0 to C3.
When the column selection line CSLj of one of the columns C0 to C3, designated by the column address signal is set at a high potential, the column select gate of the column is turned on and the write data is latched in the data latch circuit. Similarly, the write data is latched in the data latch circuit for all columns C0 to C3.
Thereafter, the control signal TG is set at a high potential to turn on the transfer gate. The data of columns C0 to C3, which is latched in the data latch circuit, is simultaneously led to the sense amplifiers corresponding to the columns C0 to C3 at a time.
In this case, since the sense amplifiers corresponding to the columns C0 to C3 are not activated, even if the write data differs from the data of the memory cells, the potential of bitline pair BLj, BBLj is inverted in a short time.
When the control signal SEN is set at a high potential, the control signal SAP becomes at a high potential and the control signal BSAN becomes at a low potential, the sense amplifiers of the columns C0 to C3 are activated and the potential of the bitline pair BLi, BBLj is amplified. The data write in the memory cells is thus completed.
According to the DRAM having the above structure, the data to be written in all columns is latched in the data latch circuit, and the latched data is led to the sense amplifiers. Then the sense amplifiers of all columns are activated and the data is written in all columns. Accordingly, in the DRAM of this example, high-speed data write can be achieved.
However, in order to achieve the high-speed write in this DRAM, it is necessary to provide new structural elements such as the data latch circuit, transfer gate and transfer gate control circuit. This results in a drawback, in which the chip size of the DRAM increases.
As has been described above, according to the conventional semiconductor memory device, when data is to be written in memory cells of the same row and different columns, data cannot be written at high speed in all memory cells due to the timing of activation of the sense amplifiers.
This drawback may be overcome by adding a structural element such as a data latch circuit. However, the structure such as the data latch circuit requires a large area within the memory chip. This results in a drawback in which the chip size of the DRAM increases.